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24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 translator out2a sense2 vbb2 out2b enable pgnd pgnd cp1 cp2 vcp vreg ms1 charge pump reg osc & control logic out1a sense1 vbb1 out1b dir reset pgnd pgnd ref step vdd rosc 26184.28c description the a3982 is a complete stepper motor driver with built- in translator for easy operation. it is designed to operate bipolar stepper motors in full- and half-step modes, with an output drive capacity of up to 35 v and 2 a. the a3982 includes a fixed off-time current regulator which has the ability to operate in slow or mixed decay modes. the translator is the key to the easy implementation of the a3982. simply inputting one pulse on the step input drives the motor one step. there are no phase sequence tables, high frequency control lines, or complex interfaces to program. the a3982 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. the chopping control in the a3982 automatically selects the current decay mode (slow or mixed). when a signal occurs at the step input pin, the a3982 determines if that step results in a higher or lower current in each of the motor phases. if the change is to a higher current, then the decay mode is set to slow decay. if the change is to a lower current, then the current decay is set to mixed (set initially to a fast decay for a period amounting to 31.25% of the features and benefits ? low r ds(on) outputs ? automatic current decay mode detection/selection ? mixed and slow current decay modes ? synchronous rectification for low power dissipation ? internal uvlo and thermal shutdown circuitry ? crossover-current protection dmos stepper motor driver with translator continued on the next page? package: 24 pin soicw with internally fused leads (suffix lb) pin-out diagram not to scale a3982
dmos stepper motor driver with translator a3982 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fixed off-time, then to a slow decay for the remainder of the off-time). this current decay control scheme results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. internal synchronous rectification control circuitry is provided to improve power dissipation during pwm operation. internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (uvlo), and crossover-current protection. special power-on sequencing is not required. the a3982 is supplied in a 24-pin wide-body soic (package lb) with internally-fused power ground leads for enhanced thermal dissipation. it is lead (pb) free, with 100% matte tin plated leadframe. description (continued) absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 35 v logic input voltage v in ?0.3 to 7 v sense voltage v sense 0.5 v reference voltage v ref 4v output current i out output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150c. 2 a operating ambient temperature t a range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing* package a3982slb-t 31 pieces per tube 24-pin wide soic with pins 6 and 7, and 18 and 19, fused internally a3982slbtr-t 1000 pieces per reel *contact allegro for additional packing options
dmos stepper motor driver with translator a3982 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram sense1 sense2 vreg vcp cp2 control logic dac vdd pwm latch blanking mixed decay dac step dir reset ms1 pwm latch blanking mixed decay current regulator cp1 charge pump r s2 r s1 vbb1 out1a out1b vbb2 out2a out2b 0.1 f v ref translator gate drive dmos full bridge dmos full bridge 0.1 f 0.22 f osc rosc ref enable
dmos stepper motor driver with translator a3982 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 at t a = 25c, v bb = 35 v (unless otherwise noted) 1 negative current is defined as coming out of (sourcing from) the specified device pin. 2 typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. performance may vary for individual units, within the specified maximum and minimum limits. 3 err i = (i trip ? i prog ) i prog , where i prog = %i tripmax ? i tripmax . characteristics symbol test conditions min. typ. 2 max. units output drivers load supply voltage range v bb operating 8 ? 35 v logic supply voltage range v dd operating 3.0 ? 5.5 v output on resistance r dson source driver, i out = ?1.5 a ? 0.370 0.460 sink driver, i out = 1.5 a ? 0.330 0.380 body diode forward voltage v f source diode, i f = ?1.5 a ? ? 1.2 v sink diode, i f = 1.5 a ? ? 1.2 v motor supply current i bb f pwm < 50 khz ? ? 4 ma operating, outputs disabled ? ? 2 ma logic supply current i dd f pwm < 50 khz ? ? 8 ma outputs off ? ? 5 ma control logic logic input voltage v in(1) v dd ? 0.7 ??v v in(0) ?? v dd ? 0.3 v logic input current i in(1) v in = v dd ? 0.7 ?20 <1.0 20 a i in(0) v in = v dd ? 0.3 ?20 <1.0 20 a input hysteresis v hys(in) 150 300 500 mv blank time t blank 0.7 1 1.3 s fixed off-time t off osc > 3 v 20 30 40 s r osc = 25 k 23 30 37 s reference input voltage range v ref 0?4v reference input current i ref ?3 0 3 a current trip-level error 3 err i v ref = 2 v, %i tripmax = 70.71% ? ? 5 % v ref = 2 v, %i tripmax = 100.00% ? ? 5 % crossover dead time t dt 100 475 800 ns protection thermal shutdown temperature t j ? 165 ? c thermal shutdown hysteresis t jhys ?15?c uvlo enable threshold uv lo v dd rising 2.35 2.7 3 v uvlo hysteresis uv hys 0.05 0.10 ? v
dmos stepper motor driver with translator a3982 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja one-layer pcb, one-sided with copper limited to solder pads 77 oc/w one-layer pcb, two-sided with copper limited to solder pads and 3.57 in. 2 of copper area on each side, connected to pgnd pins 45 oc/w four-layer pcb, based on jedec standard 35 oc/w *additional thermal information available on allegro web site. temperature, t a (c) power dissipation, p d (w) 0 0.50 1.50 2.00 2.50 3.00 3.50 4.00 1.00 20 40 60 80 100 120 140 160 power dissipation versus ambient temperature r ja = 35 o c / w r ja = 45 oc/w r ja = 77 oc / w
dmos stepper motor driver with translator a3982 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 1. logic interface timing diagram step t a t d t c ms1, reset, or dir t b table 1. stepping resolution truth table ms1 step resolution excitation mode l full step 2 phase h half step 1-2 phase time duration symbol typ. unit step minimum, high pulse width t a 1 s step minimum, low pulse width t b 1 s setup time, input change to step t c 200 ns hold time, input change to step t d 200 ns
dmos stepper motor driver with translator a3982 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description device operation. the a3982 is a complete stepper motor driver with a built-in translator for easy operation with minimal control lines. it is designed to operate bipolar stepper motors in full- and half-step modes. the currents in each of the two output full-bridges and all of the n-channel dmos fets are regulated with fixed off-time pmw (pulse width modulated) control circuitry. at each step, the current for each full-bridge is set by the value of its external current- sense resistor (r s1 or r s2 ), a reference voltage (v ref ), and the output voltage of its dac (which in turn is controlled by the output of the translator). at power-on or reset, the translator sets the dacs and the phase current polarity to the initial home state (shown in figures 2 and 3), and the current regulator to mixed decay mode for both phases. when a step command signal occurs on the step input, the translator automatically sequences the dacs to the next level and current polarity. (see table 2 for the current-level sequence.) the step resolution is set by input ms1 , as shown in table 1. when stepping, if the new output levels of the dacs are lower than their previous output levels, then the decay mode for the active full-bridge is set to mixed. if the new output levels of the dacs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to slow. this automatic current decay selection improves step- ping performance by reducing the distortion of the current waveform that results from the back emf of the motor. reset input (reset). the reset input sets the translator to a predefined home state (shown in figures 2 and 3), and turns off all of the dmos outputs. all step inputs are ignored until the reset input is set to high. step input (step) . a low-to-high transition on the step input sequences the translator and advances the motor one increment. the translator controls the input to the dacs and the direction of current flow in each winding. the size of the increment is determined by input ms1 , as shown in table 1. direction input (dir). this determines the direction of rotation of the motor. when low, the direction will be clock- wise and when high, counterclockwise. changes to this input do not take effect until the next step rising edge. internal pwm current control. each full-bridge is controlled by a fixed off-time pwm current control circuit that limits the load current to a desired value, i trip . ini- tially, a diagonal pair of source and sink dmos outputs are enabled and current flows through the motor winding and the current sense resistor, r s x . when the voltage across r s x equals the dac output voltage, the current sense compara- tor resets the pwm latch. the latch then turns off either the source dmos fet (when in slow decay mode) or the sink and source dmos fets (when in mixed decay mode). the maximum value of current limiting is set by the selec- tion of r s x and the voltage at the vref pin. the transcon- ductance function is approximated by the maximum value of current limiting, i tripmax (a), which is set by i tripmax = v ref / ( 8 ? r s ) where r s is the resistance of the sense resistor ( ) and v ref is the input voltage on the ref pin (v). the dac output reduces the v ref output to the current sense comparator in precise steps, such that i trip = (%i tripmax / 100) i tripmax (see table 2 for %i tripmax at each step.) it is critical that the maximum rating (0.5 v) on the sense1 and sense2 pins is not exceeded. fixed off-time. the internal pwm current control cir- cuitry uses a one-shot circuit to control the duration of time that the dmos fets remain off. the one shot off-time, t off , functional description
dmos stepper motor driver with translator a3982 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com is determined by the selection of an external resistor con- nected from the rosc timing pin to ground. if the rosc pin is tied to an external voltage > 3 v, then t off defaults to 30 s. the rosc pin can be safely connected to the vdd pin for this purpose. the value of t off ( s) is approximately t off r osc 825 blanking. this function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. the comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. the blank time, t blank ( s), is approximately t blank 1 s charge pump (cp1 and cp2). the charge pump is used to generate a gate supply greater than that of vbb for driving the source-side dmos gates. a 0.1 f ceramic capacitor, should be connected between cp1 and cp2. in addition, a 0.1 f ceramic capacitor is required between vcp and vbb, to act as a reservoir for operating the high-side dmos gates. vreg (vreg) . this internally-generated voltage is used to operate the sink-side dmos outputs. the vreg pin must be decoupled with a 0.22 f ceramic capacitor to ground. vreg is internally monitored. in the case of a fault condition, the dmos outputs of the a3982 are disabled. enable input (enable) . this input turns on or off all of the dmos outputs. when set to a logic high, the outputs are disabled. when set to a logic low, the internal control enables the outputs as required. the translator inputs step, dir, and ms1, as well as the internal sequencing logic, all remain active, independent of the enable input state. shutdown. in the event of a fault, overtemperature (excess t j ) or an undervoltage (on vcp), the dmos out- puts of the a3982 are disabled until the fault condition is removed. at power-on, the uvlo (undervoltage lockout) circuit disables the dmos outputs and resets the translator to the home state. mixed decay operation. the bridge can operate in mixed decay mode, depending on the step sequence, as shown in figures 3 thru 5. as the trip point is reached, the a3982 initially goes into a fast decay mode for 31.25% of the off-time, t off . after that, it switches to slow decay mode for the remainder of t off . synchronous rectification . when a pwm-off cycle is triggered by an internal fixed?off-time cycle, load current recirculates according to the decay mode selected by the control logic. this synchronous rectification feature turns on the appropriate fets during current decay, and effectively shorts out the body diodes with the low dmos r dson . this reduces power dissipation significantly, and can eliminate the need for external schottky diodes in many applications. turning off syn chronous rectification prevents the reversal of the load current when a zero-current level is detected.
dmos stepper motor driver with translator a3982 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com home microstep position home microstep position 100.00 70.71 ?70.71 0.00 ?100.00 100.00 70.71 ?70.71 0.00 ?100.00 phase 2 i out2a direction = h (%) phase 1 i out1a direction = h (%) step slow mixed slow mixed slow mixed mixed slow mixed slow mixed slow slow phase 2 i out2a direction = h (%) phase 1 i out1a direction = h (%) step home microstep position home microstep position 100.00 70.71 ?70.71 0.00 ?100.00 100.00 70.71 ?70.71 0.00 ?100.00 slow slow figure 3. decay modes for half-step increments figure 2. decay mode for full-step increments table 2. step sequencing settings home step position at step angle 45o; dir = h full step # half step # phase 1 current [% i tripmax ] (%) phase 2 current [% i tripmax ] (%) step angle (o) 1 100.00 0.00 0.0 1 2 70.71 70.71 45.0 3 0.00 100.00 90.0 2 4 ?70.71 70.71 135.0 5 ?100.00 0.00 180.0 3 6 ?70.71 ?70.71 225.0 7 0.00 ?100.00 270.0 4 8 70.71 ?70.71 315.0
dmos stepper motor driver with translator a3982 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin list table name description number out2a dmos full bridge 2 output a 1 sense2 sense resistor for bridge 2 2 vbb2 load supply 3 out2b dmos full bridge 2 output b 4 enable logic input 5 pgnd power ground 6 pgnd power ground 7 cp1 charge pump capacitor 1 8 cp2 charge pump capacitor 2 9 vcp reservoir capacitor 10 vreg regulator decoupling 11 ms1 logic input 12 reset logic input 13 rosc timing set 14 vdd logic supply 15 step logic input 16 ref current trip reference voltage input 17 pgnd power ground 18 pgnd power ground 19 dir logic input 20 1out1b dmos full bridge 1 output b 21 vbb1 load supply 22 sense1 sense resistor for bridge 1 23 out1a dmos full bridge 1 output a 24
dmos stepper motor driver with translator a3982 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com lb package, 24-pin wide body soic copyright ?2005-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com 1.27 0.25 b reference pad layout (reference ipc soic127p1030x265-24m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b 0.20 0.10 0.41 0.10 2.20 0.65 9.60 1.27 2 1 24 a 15.400.20 2.65 max 10.300.33 7.500.10 c seating plane c 0.10 24x for reference only pins 6 and 7, and 18 and 19 internally fused dimensions in millimeters (reference jedec ms-013 ad) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area gauge plane seating plane pcb layout reference view 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 2 1 24

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